(1) Field of the Invention
The present invention relates to a capacitor structure and fabrication for high-density integrated circuits, and more particularly relates to a method for making a metal insulator-metal (MIM) capacitor having a high-dielectric-constant k. The capacitor structure uses a novel patterned dummy layer formed from an insulating material. The height of a patterned dummy layer is used to fine-tune the capacitance for the electrical circuit requirements. The patterned dummy layer acts as a template for making the capacitor without partaking in the electrical properties of the capacitor.
(2) Description of the Prior Art
Capacitors on semiconductor chips are used for various integrated circuit applications. One application is for providing storage capacitors on dynamic random access memory (DRAM) circuits. As the minimum feature size of devices decreases to dimensions less than 0.25 micrometer (mm) and the storage capacitors decrease in size (area), it is necessary to increase the capacitance. One method is to make a stacked capacitor having a third dimension (height) Which increases the capacitor area without increasing the area occupied by the capacitor on the chip. However, as the height of the stacked capacitors increases and the topography gets rougher, it becomes increasingly difficult to form high-resolution patterns over the rough topography during subsequent processing. One approach to circumvent this problem is to use planarizing techniques to form a planar insulating layer over the capacitor. However, this approach requires additional processing complexity as well as increased manufacturing cost.
Another method for increasing the capacitance without increasing the capacitor height is to use a high-dielectric-constant material, such as tantalum pentoxide (Ta2O5), as the interelectrode dielectric film between the capacitor electrodes. Typically these two approaches are used in combination to satisfy the high-capacitance requirements while maintaining an acceptable topography.
Numerous methods have been reported in the literature for making high-dielectric MIM stacked capacitors. In U.S. Pat. No. 6,277,702 B1 to Chun et al., a method is described for forming a reliable MIM capacitor having a polysilicon capacitor storage node and using an interelectrode high-k dielectric film. To avoid interface problems that can cause leakage problems between the polysilicon and the high-k film, a transition metal such as platinum (Pt) is used. Then to prevent the Pt from reacting with the polysilicon capacitor storage nods, a barrier layer is required. In U.S. Pat. No. 6,084,765 to Lee, the capacitor storage node is formed from a transition metal. In this approach a diffusion barrier layer is formed over the node contact and a thick transition metal capacitor storage nods is formed on the barrier layer over the node contact. However, to electrically isolate the barrier layer from the high-k film at the edge, the transition metal layer is recessed, and an insulating layer such as Al2O3 or Ta2O5 is formed in the recess at the edge. To achieve higher capacitance it is also necessary to increase the height of the capacitor storage node, which requires etching a thick, more exotic material transition metal, such as Pt, ruthenium (Ru) or iridium (Ir), which is difficult to do. In U.S. Pat. No. 5,994,197 to Liao, a method is described for making DRAM capacitors with increased capacitance. A node contact is formed in a thick insulating layer and a trench is etched in the insulator around the node contact to increase the area of the capacitor made thereon. U.S. Pat. No. 5,877,062 to Horli describes a method for making a stacked MIM capacitor similar to U.S. Pat. No. 6,084,765 to Lee, and has similar shortcomings. Kim et al., U.S. Pat. No. 6,232,133 B1, describes a method for making a ferroelectric capacitor that does not use the sidewalls of a capacitor storage node to increase and control the capacitance.
There is still a need in the semiconductor industry to form stacked metal-insulator-metal (MIM) capacitor structures with high capacitance while reducing process complexity and improving product yield.